Various improvements to v0.9
- Pulldown on DE - Buttons - RX/TX LEDs - More pins on J7
This commit is contained in:
Lauren Lagarde
parent
cfac69c1c5
commit
68d11392bf
4 changed files with 6858 additions and 40128 deletions
102
LARPANet_STM32G030_Inline.kicad_dru
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102
LARPANet_STM32G030_Inline.kicad_dru
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@ -0,0 +1,102 @@
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(version 1)
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#Kicad 7
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# 2-layer, 1oz copper
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(rule "Minimum Trace Width (outer layer)"
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(constraint track_width (min 5mil))
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(layer outer)
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(condition "A.Type == 'track'"))
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(rule "Minimum Trace Spacing (outer layer)"
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(constraint clearance (min 5mil))
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(layer outer)
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(condition "A.Type == 'track' && B.Type == A.Type"))
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# 4-layer
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(rule "Minimum Trace Width and Spacing (inner layer)"
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(constraint track_width (min 3.5mil))
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(layer inner)
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(condition "A.Type == 'track'"))
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(rule "Minimum Trace Spacing (inner layer)"
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(constraint clearance (min 3.5mil))
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(layer inner)
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(condition "A.Type == 'track' && B.Type == A.Type"))
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# silkscreen (Kicad 7 only)
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(rule "Minimum Text"
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(constraint text_thickness (min 0.15mm))
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(constraint text_height (min 1mm))
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(layer "?.Silkscreen"))
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(rule "Pad to Silkscreen"
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(constraint silk_clearance (min 0.15mm))
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(layer outer)
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(condition "A.Type == 'pad' && (B.Type == 'text' || B.Type == 'graphic')"))
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# edge clearance
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(rule "Trace to Outline"
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(constraint edge_clearance (min 0.3mm))
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(condition "A.Type == 'track'"))
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# This would override board outline and milled areas
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#(rule "Trace to V-Cut"
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# (constraint clearance (min 0.4mm))
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# (condition "A.Type == 'track' && B.Layer == 'Edge.Cuts'"))
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# drill/hole size
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(rule "drill hole size (mechanical)"
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(constraint hole_size (min 0.2mm) (max 6.3mm)))
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(rule "Minimum Via Hole Size"
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(constraint hole_size (min 0.2mm))
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(condition "A.Type == 'via'"))
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(rule "Minimum Via Diameter"
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(constraint via_diameter (min 0.45mm))
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(condition "A.Type == 'via'"))
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(rule "PTH Hole Size"
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(constraint hole_size (min 0.2mm) (max 6.35mm))
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(condition "A.isPlated()"))
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(rule "Minimum Non-plated Hole Size"
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(constraint hole_size (min 0.5mm))
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(condition "A.Type == 'pad' && !A.isPlated()"))
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(rule "Minimum Castellated Hole Size"
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(constraint hole_size (min 0.6mm))
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(condition "A.Type == 'pad' && A.Fabrication_Property == 'Castellated pad'"))
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# clearance
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(rule "hole to hole clearance (different nets)"
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(constraint hole_to_hole (min 0.5mm))
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(condition "A.Net != B.Net"))
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(rule "via to track clearance"
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(constraint hole_clearance (min 0.254mm))
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(condition "A.Type == 'via' && B.Type == 'track'"))
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(rule "via to via clearance (same nets)"
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(constraint hole_to_hole (min 0.254mm))
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(condition "A.Type == 'via' && B.Type == A.Type && A.Net == B.Net"))
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(rule "pad to pad clearance (with hole, different nets)"
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(constraint hole_to_hole (min 0.5mm))
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(condition "A.Type == 'pad' && B.Type == A.Type && A.Net != B.Net"))
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(rule "pad to pad clearance (without hole, different nets)"
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(constraint clearance (min 0.127mm))
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(condition "A.Type == 'pad' && B.Type == A.Type && A.Net != B.Net"))
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(rule "NPTH to Track clearance)"
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(constraint hole_clearance (min 0.254mm))
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(condition "A.Pad_Type == 'NPTH, mechanical' && B.Type == 'track'"))
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(rule "PTH to Track clearance)"
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(constraint hole_clearance (min 0.33mm))
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(condition "A.isPlated() && B.Type == 'track'"))
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(rule "Pad to Track clearance)"
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(constraint clearance (min 0.2mm))
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(condition "A.isPlated() && B.Type == 'track'"))
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File diff suppressed because it is too large
Load diff
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@ -6,12 +6,12 @@
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"apply_defaults_to_fp_fields": false,
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"apply_defaults_to_fp_shapes": false,
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"apply_defaults_to_fp_text": false,
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"board_outline_line_width": 0.1,
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"copper_line_width": 0.2,
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"board_outline_line_width": 0.0381,
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"copper_line_width": 0.254,
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"copper_text_italic": false,
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"copper_text_size_h": 1.5,
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"copper_text_size_v": 1.5,
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"copper_text_thickness": 0.3,
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"copper_text_size_h": 1.524,
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"copper_text_size_v": 1.524,
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"copper_text_thickness": 0.3048,
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"copper_text_upright": false,
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"courtyard_line_width": 0.05,
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"dimension_precision": 4,
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@ -30,7 +30,7 @@
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"fab_text_size_v": 1.0,
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"fab_text_thickness": 0.15,
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"fab_text_upright": false,
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"other_line_width": 0.15,
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"other_line_width": 0.1,
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"other_text_italic": false,
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"other_text_size_h": 1.0,
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"other_text_size_v": 1.0,
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@ -41,11 +41,11 @@
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"height": 2.5,
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"width": 2.5
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},
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"silk_line_width": 0.15,
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"silk_line_width": 0.1524,
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"silk_text_italic": false,
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"silk_text_size_h": 1.0,
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"silk_text_size_v": 1.0,
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"silk_text_thickness": 0.15,
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"silk_text_size_h": 0.8128,
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"silk_text_size_v": 0.8128,
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"silk_text_thickness": 0.1524,
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"silk_text_upright": false,
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"zones": {
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"min_clearance": 0.5
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@ -68,7 +68,7 @@
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"connection_width": "warning",
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"copper_edge_clearance": "error",
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"copper_sliver": "warning",
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"courtyards_overlap": "ignore",
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"courtyards_overlap": "error",
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"diff_pair_gap_out_of_range": "error",
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"diff_pair_uncoupled_length_too_long": "error",
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"drill_out_of_range": "error",
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@ -95,9 +95,9 @@
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"padstack": "warning",
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"pth_inside_courtyard": "ignore",
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"shorting_items": "error",
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"silk_edge_clearance": "ignore",
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"silk_over_copper": "ignore",
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"silk_overlap": "ignore",
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"silk_edge_clearance": "warning",
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"silk_over_copper": "warning",
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"silk_overlap": "warning",
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"skew_out_of_range": "error",
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"solder_mask_bridge": "error",
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"starved_thermal": "error",
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@ -117,19 +117,19 @@
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"max_error": 0.005,
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"min_clearance": 0.0,
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"min_connection": 0.0,
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"min_copper_edge_clearance": 0.0,
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"min_copper_edge_clearance": 0.5,
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"min_hole_clearance": 0.25,
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"min_hole_to_hole": 0.25,
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"min_microvia_diameter": 0.2,
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"min_microvia_drill": 0.1,
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"min_microvia_diameter": 0.0,
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"min_microvia_drill": 0.0,
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"min_resolved_spokes": 2,
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"min_silk_clearance": 0.0,
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"min_text_height": 0.8,
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"min_text_thickness": 0.08,
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"min_through_hole_diameter": 0.3,
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"min_track_width": 0.0,
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"min_track_width": 0.127,
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"min_via_annular_width": 0.1,
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"min_via_diameter": 0.5,
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"min_via_diameter": 0.6,
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"solder_mask_clearance": 0.0,
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"solder_mask_min_width": 0.0,
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"solder_mask_to_copper_clearance": 0.0,
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@ -180,8 +180,11 @@
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],
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"track_widths": [
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0.0,
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0.35,
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0.5,
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0.15,
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0.2,
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0.4,
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0.6,
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0.8,
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1.0
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],
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"tuning_pattern_settings": {
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@ -214,6 +217,14 @@
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{
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"diameter": 0.0,
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"drill": 0.0
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},
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{
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"diameter": 0.6,
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"drill": 0.3
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},
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{
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"diameter": 0.9,
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"drill": 0.4
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}
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],
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"zones_allow_external_fillets": false
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@ -455,19 +466,19 @@
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"classes": [
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{
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"bus_width": 12,
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"clearance": 0.2,
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"diff_pair_gap": 0.25,
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"clearance": 0.127,
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"diff_pair_gap": 0.254,
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"diff_pair_via_gap": 0.25,
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"diff_pair_width": 0.2,
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"diff_pair_width": 0.1524,
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"line_style": 0,
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"microvia_diameter": 0.3,
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"microvia_drill": 0.1,
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"microvia_diameter": 0.6858,
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"microvia_drill": 0.3302,
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"name": "Default",
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"pcb_color": "rgba(0, 0, 0, 0.000)",
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"schematic_color": "rgba(0, 0, 0, 0.000)",
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"track_width": 0.25,
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"via_diameter": 0.8,
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"via_drill": 0.4,
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"track_width": 0.127,
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"via_diameter": 0.6,
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"via_drill": 0.3,
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"wire_width": 6
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}
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],
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File diff suppressed because it is too large
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